1. Field of the Invention
The present invention relates to a bit mask generator for generating a bit mask pattern of a plurality of bits used in pasting in the field of graphics.
2. Description of the Related Art
In the field of graphics of a bit mask system, in order to paint a given graphic pattern, a pattern must be formatted such that logic "1"s in n-bit (n is a positive integer) data are paired, and logic "1"s are inserted between the pairs. For example, n-bit input data is given as b0, b1, . . . , b(n-1), as shown in FIG. 8A. In this case, a bit mask pattern given by c0, c1, . . . , c(n-1) shown in FIG. 8B can be generated by exclusive OR products (to be referred to as XOR products hereinafter) as follows: ##EQU1## Equations (1) are equivalent to equations (2): ##EQU2##
When calculations defined by equations (2) are to be performed by a combination circuit, a circuit as shown in FIG. 9 is used. In this circuit, bit data c1 is generated when bit data c0 (=b0) and b1 are input to XOR gate 30-0. Bit data c2 is generated when bit data c1 and b2 are input to XOR gate 30-1. Similarly, bit data c(n-1) is generated when bit data c(n-2) and b(n-1) are input to XOR gate 30-(n-1).
In a conventional circuit shown in FIG. 9, a maximum of (n-1) XOR gates must be used to produce pattern c(i) from input pattern bi (i=0, 1, . . . ,n-1). If the delay time of each XOR gate is given as .tau., a total delay time is (n-1) x.tau.. In a conventional arrangement, when the number of bits constituting input data is increased, the time required for generating a mask pattern is prolonged, and mask patterns cannot be generated at high speed.